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CY7C1328G: 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM | Cypress Semiconductor

CY7C1328G: 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM

Last Updated: 
Nov 20, 2016
Version: 
*P

4-Mbit (256 K × 18) Pipelined DCD Sync SRAM

Features

  • Registered inputs and outputs for pipelined operation
  • Optimal for performance (double-cycle deselect)
    • Depth expansion without wait state
  • 256 K × 18 common I/O architecture
  • 3.3 V core power supply (VDD)
  • 3.3 V/2.5 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 4.0 ns (for 133-MHz device)
  • Provide high-performance 3-1-1-1 access rate
  • For more, see pdf
     

Functional Description

The CY7C1328G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:B], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.