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CY7C1319KV18, CY7C1321KV18: 18-Mbit DDR II SRAM Four-Word Burst Architecture | Cypress Semiconductor

CY7C1319KV18, CY7C1321KV18: 18-Mbit DDR II SRAM Four-Word Burst Architecture

Last Updated: 
Jan 26, 2016
Version: 
*J

18-Mbit DDR II SRAM Four-Word Burst Architecture

Features

  • 18 Mbit density (1 M x 18, 512 K x 36)
  • 333-MHz clock for high bandwidth
  • Four-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
  • Two input clocks (K and K) for precise DDR timing
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
  • For more, see pdf
     

Functional Description

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.