You are here

CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, CY7C1315KV18: 18-Mbit QDR® II SRAM Four-Word Burst Architecture | Cypress Semiconductor

CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, CY7C1315KV18: 18-Mbit QDR® II SRAM Four-Word Burst Architecture

Last Updated: 
Dec 07, 2017
Version: 
*K

18-Mbit QDR® II SRAM Four-Word Burst Architecture

Features

  • Separate independent read and write data ports
    • Supports concurrent transactions
  • 333-MHz clock for high bandwidth
  • Four-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • For more, see pdf

Functional Description

The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.