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CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, CY7C1314JV18: 18-Mbit QDR® II SRAM 2-Word Burst Architecture | Cypress Semiconductor

CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, CY7C1314JV18: 18-Mbit QDR® II SRAM 2-Word Burst Architecture

Last Updated: 
Jun 20, 2014
Version: 
*D

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18-Mbit QDR® II SRAM 2-Word Burst Architecture

Features

  • Separate independent read and write data ports
    • Supports concurrent transactions
  • 250 MHz clock for high bandwidth
  • 2-word burst on all accesses
  • Double Data Rate (DDR) interfaces on both read and write ports
    (data transferred at 500 MHz) at 250 MHz
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • For more, see pdf

Functional Description

The CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, and CY7C1314JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations.