CY7C1303BV25: 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture | Cypress Semiconductor
CY7C1303BV25: 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture
18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture
Separate independent read and write data ports
167 MHz clock for high bandwidth
Two word burst on all accesses
Double data rate (DDR) interfaces on both read and write ports (data transferred at 333 MHz) at 167 MHz
Two input clocks (K and K) for precise DDR timing
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
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The CY7C1303BV25 is 2.5 V synchronous pipelined SRAM equipped with QDR® architecture. QDR architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.