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CY7C1262XV18, CY7C1264XV18: 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | Cypress Semiconductor

CY7C1262XV18, CY7C1264XV18: 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Last Updated: 
Oct 30, 2015
Version: 
*F

36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Features

  • Separate independent read and write data ports
  • 450 MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
  • Available in 2.5 clock cycle latency
  • Two input clocks (K and K) for precise DDR timing
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • Data valid pin (QVLD) to indicate valid data on the output
  • Single multiplexed address input bus latches address inputs for both read and write ports
  • Separate port selects for depth expansion
  • Synchronous internally se
  • lf-timed writes
  • For more, see pdf
     

Functional Description

The CY7C1262XV18, and CY7C1264XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR® II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to  completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.