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CY7C1168KV18, CY7C1170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) | Cypress Semiconductor

CY7C1168KV18, CY7C1170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Last Updated: 
Feb 02, 2016
Version: 
*H

18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

Features

  • 18-Mbit density (1 M × 18, 512 K × 36)
  • 550-MHz clock for high bandwidth
  • Two-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
  • Available in 2.5 clock cycle latency
  • Two input clocks (K and K) for precise DDR timing
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • For more, see pdf

Functional Description

The CY7C1168KV18, and CY7C1170KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.