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CY7C09159AV: 3.3-V 8 K × 9 Synchronous Dual Port Static RAM | Cypress Semiconductor

CY7C09159AV: 3.3-V 8 K × 9 Synchronous Dual Port Static RAM

Last Updated: 
Aug 25, 2015
Version: 
*F

3.3-V 8 K × 9 Synchronous Dual Port Static RAM

Features

  • True dual-ported memory cells which allow simultaneous access of the same memory location
  • Flow-through/Pipelined device
    • 8 K × 9 organization (CY7C09159AV)
  • Three Modes
    • Flow-through
    • Pipelined
    • Burst
  • Pipelined output mode on both ports allows fast 67-MHz operation
  • 0.35-micron complementary metal oxide semiconductor (CMOS) for optimum speed/power
  • High-speed clock to data access 9 ns (max.)
  • For more, see pdf.

Functional Description

The CY7C09159AV is a high-speed synchronous CMOS 8 K × 9 dual-port static RAM. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 20 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin.