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CY7B9973V RoboClock®, High-Speed Multi-Output PLL Clock Buffer | Cypress Semiconductor

CY7B9973V RoboClock®, High-Speed Multi-Output PLL Clock Buffer

Last Updated: 
Nov 07, 2016
Version: 
*G

This product datasheet is no longer supported by Cypress. We have a new product family called CY7B991, which we recommend in its place. Please click here or contact your local sales representative for more information.

High Speed Multi-Output PLL Clock Buffer

Features

  • 10 MHz to 200 MHz output operation
  • Output-to-output skews < 350 ps
  • 13 LVTTL 50% duty cycle outputs capable of driving 50Ω terminated lines
  • Phase-locked loop (PLL) LOCK indicator
  • 3.3V LVTTL/LV differential (LVPECL) hot insertable reference inputs
  • Multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20) : (2, 4, 6, 8, 10, 12, 16, 20)
  • Operation with outputs operating at up to 10x input frequency
  • Low cycle-to-cycle jitter (< ±75 ps peak-peak)
  • Single 3.3V ± 10% supply
  • 52-pin TQFP package

Functional Description

The CY7B9973V Low Voltage PLL Clock Buffer offers user-selectable frequency control over system clock functions. This twelve output clock driver provides the system integrator with selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs. An additional output is dedicated to providing feedback information to allow the internal PLL to multiply an external reference frequency by 4, 6, 8, 10, 12, 16 or 20. The completely integrated PLL reduces jitter and simplifies board layout.