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CY7B995: 2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer | Cypress Semiconductor

CY7B995: 2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer

Last Updated: 
May 13, 2016
Version: 
*I

2.5/3.3 V 200 MHz High-Speed Multi-Phase PLL Clock Buffer

Features

  • 2.5V or 3.3V operation
  • Split output bank power supplies
  • Output frequency range: 6 MHz to 200 MHz
  • 45 ps typical cycle-cycle jitter
  • ± 2% max output duty cycle
  • Selectable output drive strength
  • Selectable positive or negative edge synchronization
  • Eight LVTTL outputs driving 50 Ω terminated lines
  • LVCMOS/LVTTL over-voltage tolerant reference input
  • For more, see pdf

Description

The CY7B995 RoboClock® is a low voltage, low power, eight-output, 200 MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high performance computer and communication systems.

The user can program both the frequency and the phase of the output banks through nF[0:1] and DS[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to feedback to achieve different reference frequency multiplication, and divide ratios and zero input-output delay.      More...