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CY7B993V, CY7B994V: High Speed Multi Phase PLL Clock Buffer | Cypress Semiconductor

CY7B993V, CY7B994V: High Speed Multi Phase PLL Clock Buffer

Last Updated: 
May 13, 2016

High Speed Multi Phase PLL Clock Buffer


  • 500 ps Max Total Timing Budget (TTB™) window
  • 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation
  • Matched Pair Output Skew < 200 ps
  • Zero Input-to-Output Delay
  • 18 LVTTL Outputs Driving 50Ω Terminated Lines
  • 16 Outputs at 200 MHz: Commercial Temperature
  • 6 Outputs at 200 MHz: Industrial Temperature
  • 3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable Reference Inputs
  • Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns
  • For more, see pdf

Functional Description

The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.These devices feature a guaranteed maximum TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process.