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CY7B991, CY7B992: Programmable Skew Clock Buffer | Cypress Semiconductor

CY7B991, CY7B992: Programmable Skew Clock Buffer

Last Updated: 
May 13, 2016

Programmable Skew Clock Buffer


  • All output pair skew <100 ps typical (250 ps maximum)
  • 3.75 MHz to 80 MHz output operation
  • User selectable output functions
    • Selectable skew to 18 ns
    • Inverted and non-inverted
    • Operation at 1⁄2 and 1⁄4 input frequency
    • Operation at 2x and 4x input frequency (input as low as 3.75 MHz)
  • Zero input to output delay
  • 50% duty cycle outputs
  • Outputs drive 50Ω terminated lines
  • Low operating current
  • 32-pin PLCC/LCC package
  • Jitter <200 ps peak-to-peak (< 25 ps RMS)

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50. They can deliver minimal and specified output skews and full swing logic levels (CY7B991 TTL or CY7B992 CMOS).