You are here

CY2XP61 125 Mhz Lvpecl Clock Generator | Cypress Semiconductor

CY2XP61 125 Mhz Lvpecl Clock Generator

Last Updated: 
Dec 31, 2015

The CY2XP61 is a PLL-based high performance clock generator that uses Cypress’s low-noise VCO technology to achieve less than 4 ps typical RMS phase jitter. The CY2XP61 uses a 1.8V
external reference clock input to generate one LVPECL output pair, which can be asynchronously enabled/disabled with an OE pin (Pin 5). The device operates at 3.3 V. Pin 5 can also be
programmed as PD#. The OE function is used to enable or disable the CLK output quickly, but it does not reduce core power consumption. The PD# function puts the device into low-power state.