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CY2XP12: Low RMS Phase Jitter Programmable LVPECL Clock Generator | Cypress Semiconductor

CY2XP12: Low RMS Phase Jitter Programmable LVPECL Clock Generator

Last Updated: 
Aug 27, 2015
Version: 
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Low RMS Phase Jitter Programmable LVPECL Clock Generator

Features

  • Programmable LVPECL clock generator
  • Low RMS phase jitter
  • Available output frequencies: 50 MHz to 700 MHz
  • Pb-free 8-Pin TSSOP package
  • Supply voltage: 3.3 V or 2.5 V
  • Industrial temperature ranges

Functional Description

The CY2XP12 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate 10 Gb Ethernet, SONET, and other high performance clock frequencies. It uses Cypress’s low noise VCO technology to achieve less than 1 ps typical RMS phase jitter, which meets both 10 Gb Ethernet and SONET jitter requirements. The CY2XP12 device has a crystal oscillator interface input and one LVPECL output pair. CY2XP12 can be programmed as Output Enable (OE), or Power Down (PD#), or Frequency Select (FS) device by configuring the pin 5. The output frequency and drive-strength of this device are also programmable.The device can be programmed either to operate at 3.3 V or at 2.5 V.