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Cy2xl13, Low-noise Lvds Clock Generator | Cypress Semiconductor

Cy2xl13, Low-noise Lvds Clock Generator

Last Updated: 
Dec 31, 2015

The CY2XL13 is a phase-locked loop (PLL)-based high-performance clock generator that uses Cypress’s low-noise voltage control oscillator (VCO) technology to achieve less than 1-pstypical RMS phase jitter. The CY2XL13  uses an external crystal reference input to generate one LVDS output pair, which can be asynchronously enabled/disabled with an OE pin. The
device operates at 3.3 V or 2.5 V.

  • Output: One low-voltage differential signal (LVDS) output pair
  • Output frequency: 125 MHz
  • Input: 25-MHz external crystal
  • RMS phase jitter: At 125 MHz (12 kHz to 20 MHz offset): 0.65 ps typical
  • Package: Pb-free 8-pin thin shrunk small outline package (TSSOP)
  • Supply voltage: 3.3 V or 2.5 V
  • Temperature range: Commercial or industrial