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CY2DP1510: 1:10 LVPECL Fanout Buffer with Selectable Clock Input | Cypress Semiconductor

CY2DP1510: 1:10 LVPECL Fanout Buffer with Selectable Clock Input

Last Updated: 
Jun 19, 2016
Version: 
*Q

1:10 LVPECL Fanout Buffer with Selectable Clock Input

Features

  • Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to 10 LVPECL output pairs
  • Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input
  • 40-ps maximum output-to-output skew
  • 600-ps maximum propagation delay
  • 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
  • Up to 1.5-GHz operation
  • 32-pin thin quad flat pack (TQFP) package
  • 2.5-V or 3.3-V operating voltage
  • Commercial and industrial operating temperature range

Functional Description

The CY2DP1510 is an ultra-low noise, low skew, low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1510 can select between two separate differential (LVPECL, LVDS, HCSL, or CML) input clock pairs using the IN_SEL pin. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.