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CY2DP1504: 1:4 LVPECL Fanout Buffer with Selectable Clock Input | Cypress Semiconductor

CY2DP1504: 1:4 LVPECL Fanout Buffer with Selectable Clock Input

Last Updated: 
Nov 27, 2017
Version: 
*O

1:4 LVPECL Fanout Buffer with Selectable Clock Input

Features

  • Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVPECL output pairs
  • Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input
  • 30 ps maximum output-to-output skew
  • 480-ps maximum propagation delay
  • 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
  • Up to 1.5-GHz operation
  • Synchronous clock enable function
  • 20-pin TSSOP
  • 2.5-V or 3.3-V operating voltage
  • Commercial and industrial operating temperature range

Functional Description

The CY2DP1504 is an ultra-low noise, low-skew, low-propagation delay, 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1504 can select between separate differential (LVPECL, LVDS, HCSL, or CML) input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.