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CY2DM1502, 1:2 CML Fanout Buffer with Selectable Clock Input | Cypress Semiconductor

CY2DM1502, 1:2 CML Fanout Buffer with Selectable Clock Input

Last Updated: 
Nov 20, 2017
Version: 
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CY2DM1502: 1:2 CML Fanout Buffer with Selectable Clock Input

Features

  • One current mode logic (CML), High-speed current steering logic (HCSL), or low-voltage positive emitter-coupled logic (LVPECL) input pair distributed to two CML output pairs
  • 20-ps maximum output-to-output skew
  • 480-ps maximum propagation delay
  • 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
  • Up to 1.5 GHz operation
  • 8-Pin thin shrunk small outline package (TSSOP) package
  • 2.5-V or 3.3-V operating voltage[1]
  • Commercial and industrial operating temperature range

Functional Description

The CY2DM1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 CML, HCSL, or LVPECL to CML fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.