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CY2DL1510, 1:10 Differential LVDS Fanout Buffer | Cypress Semiconductor

CY2DL1510, 1:10 Differential LVDS Fanout Buffer

Last Updated: 
May 12, 2016

1:10 Differential LVDS Fanout Buffer 


  • Low-voltage differential signal (LVDS) input with on-chip 100-Ω input termination resistor
  • Ten differential LVDS outputs
  • 40-ps maximum output-to-output skew
  • 600-ps maximum propagation delay
  • 0.11ps maximum additive RMS phase jitter at 156.25 MHz (12kHz to 20MHz offset)
  • Up to 1.5GHz operation
  • Synchronous clock enable function
  • 32-pin thin quad flat pack (TQFP) package
  • 2.5V or 3.3V operating voltage
  • Commercial and industrial operating temperature range

Functional Description

The CY2DL1510 is an ultra-low noise, low-skew, low-propagation delay 1:10 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The on-chip 100 Ω input termination resistor reduces board component count, while the synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 GHz.