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CY24271: Rambus® XDR™ Clock Generator | Cypress Semiconductor

CY24271: Rambus® XDR™ Clock Generator

Last Updated: 
Jun 24, 2016
Version: 
*F

Rambus® XDR™ Clock Generator

Features

  • Meets Rambus® Extended Data Rate (XDR™) clocking requirements
  • 25 ps typical cycle-to-cycle jitter
    • 135 dBc/Hz typical phase noise at 20 MHz offset
  • 100 or 133 MHz differential clock input
  • 300-800 MHz high speed clock support
  • Quad (open drain) differential output drivers
  • Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4
  • Spread Aware™
  • 2.5 V operation
  • 28-pin TSSOP package

SMBus Protocol

The CY24271 is a slave receiver supporting operations in the word and byte modes described in sections 5.5.4 and 5.5.5 of the SMBus Specification 2.0.

DC specifications are modified to RAMBUS standard to support 1.8, 2.5, and 3.3 volt devices. Time-out detection and packet error protocol SMBus features are not supported.