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CY2305C/CY2309C, 3.3 V ZERO DELAY CLOCK BUFFER | Cypress Semiconductor


Last Updated: 
May 11, 2016

3.3 V Zero Delay Clock Buffer


  • 10 MHz to 100–133 MHz operating range
  • Zero input and output propagation delay
  • Multiple low skew outputs
  • One input drives five outputs (CY2305C)
  • One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
  • 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
  • Test mode to bypass phase locked loop (PLL) (CY2309C) only
  • Available in space saving 16-pin 150 Mil small outline integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
  • 3.3 V operation
  • Commercial, industrial and automotive-A flows available

Functional Description

The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309.

The CY2309C is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.