You are here

CY2213: High Frequency Programmable PECL Clock Generator | Cypress Semiconductor

CY2213: High Frequency Programmable PECL Clock Generator

Last Updated: 
Aug 26, 2015
Version: 
*J

High-Frequency Programmable PECL Clock Gener ator

Features
 
  • Jitter peak-peak (TYPICAL) = 35 ps
  • LVPECL output
  • Default Select option
  • Serially-configurable multiply ratios
  • Output edge-rate control
  • 16-pin TSSOP
  • High frequency
  • 3.3V operation
  • For more, see pdf
     
Introduction

The CY2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2213 is a slave device and can either read or write information on the dataline upon request from the master device.