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CY14V101Q3: 1 Mbit (128 K x 8) Serial SPI nvSRAM | Cypress Semiconductor

CY14V101Q3: 1 Mbit (128 K x 8) Serial SPI nvSRAM

Last Updated: 
Aug 19, 2015


  • 1-Mbit nonvolatile static random access memory (nvSRAM)
    Internally organized as 128 K × 8
    • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE)
    • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
    • Automatic STORE on power-down with a small capacitor
  • High reliability
    • Infinite read, write, and RECALL cycles
    • 1 million STORE cycles to QuantumTrap
    • Data retention: 20 years
  • High speed serial peripheral interface (SPI)
    • 30 MHz clock rate
    • Supports SPI mode 0 (0,0) and mode 3 (1,1)
  • Write protection
    • Hardware protection using Write Protect (WP) pin
    • Software protection using Write Disable instruction
    • Software block protection for 1/4,1/2, or entire array
  • Low power consumption
    • Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
    • Average active current of 10 mA at 30 MHz operation
  • Industry standard configurations
    • Industrial temperature
    • 16-pin small outline integrated circuit (SOIC) package
    • Restriction of hazardous substances (RoHS) compliant

Functional Overview

The Cypress CY14V101Q3 combines a 1 Mbit nvSRAM with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cell provides highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). Both STORE and RECALL operations can also be initiated by the user through SPI instruction.