You are here

CY14C256Q, CY14B256Q, CY14E256Q: 256-Kbit (32 K × 8) SPI nvSRAM | Cypress Semiconductor

CY14C256Q, CY14B256Q, CY14E256Q: 256-Kbit (32 K × 8) SPI nvSRAM

Last Updated: 
Aug 28, 2015


  • 256-Kbit nonvolatile static random access memory (nvSRAM) internally organized as 32 K × 8
    • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
    • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
    • Support automatic STORE on power-down with a small capacitor (except for CY14X256Q1A)
  • High reliability
    • Infinite read, write, and RECALL cycles
    • 1million STORE cycles to QuantumTrap
    • Data retention: 20 years at 85 °C
  • 40 MHz and 104 MHz High speed serial peripheral interface (SPI)
    • 40 MHz clock rate SPI write and read with zero cycle delay
    • 104 MHz clock rate SPI write and SPI read (with special fast read instructions)
    • Supports SPI mode 0 (0,0) and mode 3 (1,1)
  • SPI access to special functions
    • Nonvolatile STORE/RECALL
    • 8-byte serial number
    • Manufacturer ID and Product ID
    • Sleep mode
  • Write protection
    • Hardware protection using Write Protect (WP) pin
    • Software protection using Write Disable instruction
    • Software block protection for 1/4, 1/2, or entire array
  • Low power consumption
    • Average active current of 3 mA at 40 MHz operation
    • Average standby mode current of 150 μA
    • Sleep mode current of 8 μA
  • Industry standard configurations
    • Operating voltages:
      • CY14C256Q: VCC = 2.4 V to 2.6 V
      • CY14B256Q: VCC = 2.7 V to 3.6 V
      • CY14E256Q: VCC = 4.5 V to 5.5 V
    • Industrial temperature
    • 8- and 16-pin small outline integrated circuit (SOIC) package
    • Restriction of hazardous substances (RoHS) compliant

Functional Overview

The Cypress CY14X256Q combines a 256-Kbit nvSRAM with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X256Q1A). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.