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Watch Counter (PDL_WC) | Cypress Semiconductor

Watch Counter (PDL_WC)

Last Updated: 
Oct 19, 2016
Version: 
1.0
Features
  • 6-bit down counter
  • Prescaler generates a wide range of WC input clock frequencies
  • Supports low-power wakeup
Symbol Diagram

General Description

The Watch Counter is a 6-bit down counter that optionally generates an interrupt on underflow. The period of the counter is controlled with the reload value and the clock from the prescaler, which offers four choices (WCCK0 to WCCK3) to the Watch Counter. The prescaler is set up in firmware with an API function to select the clock source and divider for each of the WCCKn clocks.

WC Component Parameter Editor