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UART (SCB_UART_PDL) | Cypress Semiconductor

UART (SCB_UART_PDL)

Last Updated: 
Dec 13, 2017
Version: 
2.0
Features Symbol Diagram
  • Baud Rate of up to 1 Mbps
  • Detection of Framing, Parity, and Overrun Errors
  • Full Duplex, TX only, and RX only modes
  • 9-bit address mode with hardware address detection
  • Break signal detection
  • Hardware Flow control
  • Smartcard and IrDA support
  • DMA support
  • Peripheral Driver Library (PDL) Component (PDL Application Programming Interface (API) only)
 

 

General Description

The SCB_UART_PDL Component provides asynchronous communications commonly referred to as RS232 or RS485. The Component can be configured for Full Duplex, RX only, or TX only versions. It can also be configured as a SmartCard interface, or an IrDA interface.

For most use cases, you can easily configure the UART by choosing the baud rate, parity, number of data bits, and number of start bits. The most common configuration for RS232 is often listed as “8N1,” which is shorthand for eight data bits, no parity, and one stop bit. This is the default configuration for the SCB_UART_PDL Component. Therefore, in most applications you only need to set the baud rate. A second common use for UARTs is in multi-drop RS485 networks. The SCB_UART_PDL Component supports 9-bit addressing mode with hardware address detect.

UARTs have been around a long time, so there have been many physical-layer and protocol-layer variations over time. These include, but are not limited to, RS423, DMX512, MIDI, LIN bus, legacy terminal protocols. To support the commonly used UART variations, the Component provides configuration support for the number of data bits, stop bits, parity, hardware flow control, and parity generation and detection.

The SCB_UART_PDL Component is a graphical configuration entity built on top of the cy_scb driver available in the PDL. It allows schematic-based connections and hardware configuration as defined by the Component Configure dialog.