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PSoC ® Creator™ Component Datasheet - Smart I/O™ | Cypress Semiconductor

PSoC ® Creator™ Component Datasheet - Smart I/O™

Last Updated: 
Nov 15, 2017
Version: 
1.10

The Cypress Smart I/O™ component provides a programmable logic fabric interposed between a General Purpose Input/Output (GPIO) port and the connections to it from various peripherals.

Inputs to the chip from the GPIO port can be logically operated upon before being routed to the peripheral blocks and connectivity of the chip. Likewise, outputs from the peripheral blocks and internal connectivity of the chip can be logically operated upon before being routed to the GPIO port.

The programmable logic fabric of the Smart I/O component can be purely combinatorial or registered with a choice of clock selection. Its functionality is completely user-defined and each path can be selectively bypassed if certain routes are not required by the fabric.

Each Smart I/O component is associated with a particular GPIO port and consumes the port entirely. If the component is not used, then the Smart I/O functionality for that port is bypassed. The component can operate in low-power modes (Deep Sleep and Hibernate) and can wake up the chip using the port interrupt, when required.

 

Smart I/O Features

  • Provides glue logic functionality at I/O ports
  • Low-power mode (Deep Sleep and Hibernate) operation
  • Flexible array for user-defined logic functions
  • Combinatorial and clocked (registered) operation
  • Low-latency deterministic delays
  • Simple user interface for routing signals in the fabric 

  
Smart I/Os configured as digital XOR logic gates with PWM inputs to implement eight breathing LEDs
 


Smart I/Os configured as digital buffers to provide signal or clock replication of an input signal from a GPIO pin
 


Smart I/Os configured as digital OR gates to implement a priority encoder function that stores the result in the Smart I/O register for the CPU to process