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PSoC 4 Scanning SAR ADC (Scan_ADC) | Cypress Semiconductor

PSoC 4 Scanning SAR ADC (Scan_ADC)

Last Updated: 
Mar 08, 2018
Features Symbol Diagram
  • Selectable 8-, 10-, or 12-bit resolution
  • Interleaved or channel-sequential averaging in hardware
  • Up to 16-bit resolution with averaging
  • Aggregate sample rate up to 1 Msps
  • Single-ended and Differential input modes
  • Optional 2nd order switched-cap filter on channel 0
  • Scheduler optimizes settling time and clock to fit scan rate
  • Scan up to sixteen analog signals automatically
  • Four run-time selectable configurations


General Description

The Scanning SAR ADC Component gives configuration-, schematic-, and firmware-level support for the version of the Successive Approximation Register (SAR) ADC present on some members of the PSoC family. Up to sixteen analog channels (from sources dependent on the specific device) can be automatically scanned, either on demand or continuously, with the results placed in individual result registers. One of the channels may be routed through a 2nd order switched-cap filter. The scan scheduler adjusts internal sampling behavior and clock to accommodate specific settling time and overall scan rate requirements. Averaging can be applied to any channel in a scan.