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MDIO Interface | Cypress Semiconductor

MDIO Interface

Last Updated: 
Sep 23, 2016
Symbol Diagram
  • Used in conjunction with Ethernet products
  • Configurable physical address
  • Supports up to 4.4 MHz in the clock bus (mdc)
  • Compliant with IEEE 802.3 Clause 45
  • Automatically allocates memory for the register spaces that can be configured through an intuitive, easy-to-use graphical configuration GUI

General Description

The MDIO Interface component supports the Management Data Input/Output, which is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface (MII). The MII connects Media Access Control (MAC) devices with Ethernet physical layer (PHY) circuits. The component is compliant with IEEE 802.3 Clause 45.

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