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General Purpose I/O Pin (PDL_GPIO) and Fast GPIO Pin (PDL_FGPIO) | Cypress Semiconductor

General Purpose I/O Pin (PDL_GPIO) and Fast GPIO Pin (PDL_FGPIO)

Last Updated: 
Oct 25, 2016
Version: 
1.0
Features
  • Firmware access to GPIO
  • Firmware access to Fast GPIO
  • Pin-independent C macros
Symbol Diagram

General Description

The GPIO and FGPIO Components are used to enable access to pins from application firmware. Both Components use the firmware driver from the PDL GPIO module. You can assign any pin to be a Fast GPIO pin, which can read an input level and set an output level from the CPU within one cycle clock of HCLK.

The components generate C macros to enable easy initialization and control of the pins from firmware. The macro names are independent of the physical pin used for the IO and so pin changes can be made in the Design-Wide Resources Pin Editor and the project rebuilt without editing a single line of C code.

You can also configure an output pin to be readable by first enabling it as an input and then an output. This is particularly useful when you need to toggle the state of a pin.