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DMA Channel (PDL_DMA) | Cypress Semiconductor

DMA Channel (PDL_DMA)

Last Updated: 
Oct 25, 2016
Version: 
1.0
Features
  • 8 independent DMA channels
  • Trigger from Base Timer, External Interrupt, Multi-Function Serial block or ADC
  • Powerful Block, Burst and Demand transfer modes
  • Start, pause and terminate transfers from firmware
Symbol Diagram

General Description

The DMA Channel Component makes setting up DMA transfers simple and reliable with a parameter editor that presents all the important configuration options in a neat, logical way.

In firmware, all you need to do is specify the source and destination addresses before initializing the block. After that you simply trigger the transfers from firmware, or one of the supported peripherals, and the data transfer occurs without CPU intervention. You can also specify callback handlers for transfer completions and error conditions.

There are three transfer modes that give you flexibility over the scheduling of transfers. Block mode transfers multiple blocks of data with timing gaps between blocks to enable the DMA controller to switch to higher priority transfers. Burst mode is a higher priority transfer with no timing gaps so that the transfer completes before the next channel is enabled. Demand transfers are triggered from any peripheral that can raise a DMA request.

DMA Component Parameter Editor