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ADC Successive Approximation Register (ADC_SAR) | Cypress Semiconductor

ADC Successive Approximation Register (ADC_SAR)

Last Updated: 
Sep 21, 2016
Version: 
3.0

Features

  • Supports PSoC 5LP family of devices
  • 12-bit resolution at up to 1 msps maximum
  • Four power modes
  • Selectable resolution and sample rate
  • Single-ended or differential input
Symbol Diagram

General Description

The ADC Successive Approximation Register (ADC_SAR) component provides medium-speed (maximum 1-msps sampling), medium-resolution (12 bits maximum), analog-to-digital conversion.

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