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CE97089 - PSoC® 4: ADC to Memory Buffer DMA Transfer | Cypress Semiconductor

CE97089 - PSoC® 4: ADC to Memory Buffer DMA Transfer

Last Updated: 
Aug 29, 2017
Version: 
*A

This code example sets up the PSoC 4 DMA controller to transfer data from the ADC result register to an array in SRAM. A transfer is initiated each time the ADC asserts an end of conversion (EOC) signal. At the end of each DMA transfer, an interrupt is generated. The CPU implements a simple moving average filter on the data in the array and sends the results through a UART.

Every DMA channel in PSoC 4 has two descriptor structures. The descriptor comprises information regarding the source and destination address, the modes of transfer, and other specifics related to a transfer. You can choose to use one or both the descriptors in the channel. 

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