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AN89611 - PSoC® 3 and PSoC 5LP – Getting Started With Chip Scale Packages (CSP) | Cypress Semiconductor

AN89611 - PSoC® 3 and PSoC 5LP – Getting Started With Chip Scale Packages (CSP)

Last Updated: 
Apr 28, 2017
Version: 
*E

This application note provides guidelines for using Cypress PSoC® 3 and PSoC 5LP devices in wafer-level chip scale packages (CSP). Included are instructions for using the I2C bootloader that is factory installed in these devices.

Introduction

Cypress is now offering its PSoC 3 and PSoC 5LP family of products in wafer-level chip scale packages (WLCSP, or CSP for short). These devices are designed to pack the maximum mixed-signal SoC capability per cubic millimeter. They feature package sizes as small as 4.25 × 4.98 × 0.6 mm to fit into tiny spaces on very small PCBs or flexible printed circuits (FPC). However, their small size mandates special manufacturing techniques and design considerations.