You are here

AN84060 - QDR®-IV Design Guide | Cypress Semiconductor

AN84060 - QDR®-IV Design Guide

Last Updated: 
Sep 01, 2016
AN84060 describes the key features, functional description, operational modes, power calculation, and board design guidelines of QDR®-IV, Cypress’s quad data rate family of networking SRAMs. This application note also highlights the key differences among the QDR-II, QDR-II+, and QDR-IV SRAM family members.


Streaming video, cloud services, and mobile data have fueled the continuing growth of global network traffic. To support this growth, the next generation of networking systems must provide faster line rates and process millions of packets every second. Packets arrive in a random order and each packet requires several memory transactions to process. In high-performance networking systems, the flow of packets demands hundreds of millions of memory transactions every second to look up routes from a forwarding table or to update statistics.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.