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AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details | Cypress Semiconductor

AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details

Last Updated: 
Aug 22, 2017
Version: 
*F

Introduction

Cypress’s Radiation Hardened 72Mbit QDR®II+ is a source synchronous pipelined Static RAM equipped with the 1.8-V QDRII+ architecture with RadStop® technology. The QDRII+ architecture has separate data inputs and data outputs along with a common multiplexed address port. To maximize data throughput, both read and write ports are equipped with DDR interfaces which transfer data on both rising and falling edges of the clock signal. The result is that two/four bus widths of data are transferred during each clock period for Burst 2/Burst 4 configurations.