AN49081 - Requirements for Input Clock to West Bridge® Devices | Cypress Semiconductor
AN49081 - Requirements for Input Clock to West Bridge® Devices
AN49081 addresses the requirements for the input clock to West Bridge® devices that includes Antioch™, Astoria™, and TX3LP18. The conversion of phase noise specifications into equivalent RMS jitter is also discussed.
This document addresses the input clock requirements for three devices in the West Bridge® family of products: Antioch, Astoria, and TX3LP18. The computation of equivalent RMS jitter from phase noise characteristics is also discussed.