AN46982 - PLL Considerations in QDR® - II/II+/DDR-II/II+ SRAMs | Cypress Semiconductor
AN46982 - PLL Considerations in QDR® - II/II+/DDR-II/II+ SRAMs
AN46982 provides an overview of the operation of QDR-II/II+/DDR-II/II+ SRAMs in PLL disabled mode.
QDR SRAM family of devices has a phase-locked loop (PLL) within the device to synchronize the output data to the input clocks thereby enabling the device to operate at higher frequencies.
QDR-II/II+/DDR-II/II+ devices can be operated with PLL enabled or PLL disabled. This application note provides an overview of the operation of the device when the PLL is disabled.
|File Title||Language||Size||Last Updated|
|AN46982 PLL Considerations in QDR - II/II+/DDR-II/II+ SRAMs.pdf||English||292.65 KB||08/26/2015|
Need help? Ask a question and find answers in the Cypress Developer Community Forums.
Low/intermittent bandwidth users tip: Firefox and Chrome browsers will allow downloads to be resumed if your connection is lost during download.