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AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide | Cypress Semiconductor

AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide

Last Updated: 
Aug 02, 2017
Version: 
*I

Cypress Quad Data Rate™ (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 GBps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.