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AN5042 - Migrating from Cypress FLEx18 / FLEx36® / FLEx72™ Dual-Port SRAMs to FullFlex Dual-Port SRAMs | Cypress Semiconductor

AN5042 - Migrating from Cypress FLEx18 / FLEx36® / FLEx72™ Dual-Port SRAMs to FullFlex Dual-Port SRAMs

Last Updated: 
Nov 23, 2015
Version: 
*D
This is an Obsolete Application Note
The document AN5042 - Migrating from Cypress FLEx18 / FLEx36® / FLEx72™ Dual-Port SRAMs to FullFlex Dual-Port SRAMs has been marked as obsolete. The obsolete version of this application note is still available with the below description but may not be complete or valid any longer. If you have any questions or require support in regards to the below application note content, please click here and create a technical support case.

Introduction

Cypress's FLEx18 / FLEx36® / FLEx72™ portfolio of highdensity, high-performance synchronous Dual-Port SRAMs can operate at speeds up to 167 MHz. In the fast growing data communications market, the bandwidth requirements have increased. Cypress addresses these demands with its FullFlex Dual-Port SRAMs, which can operate up to 200 MHz.

 

FLEx18: CYD01S18V/ CYD02S18V/ CYD04S18V/ CYD09S18V

FLEx36: CYD02S36V/36VA

FLEx72: CYD04S72V/CYD09S72V/CYD18S72V
 

FullFlex x 18: CYD36S18V18, CYD18S18V18, CYD09S18V18

FullFlex x 36: CYD02S36V18, CYD09S36V18, CYD18S36V18, CYD36S36V18

FullFlex x 72: CYD09S72V18, CYD18S72V18, CYD36S72V18

Package:

256-ball FBGA 17mm x 17mm
484-ball FBGA 23mm x 23mm

Package:

256-ball FBGA 17mm x 17mm
484-ball FBGA 23mm x 23mm

  • Power Supply 3.3V
  • Single I/O Standard
    • LVTTL(3.3V)

     

  • Upto 167MHz in pipelined mode
  • Pipelined mode of operation
  • Burst Counter, Mask & Counter Wrap around features
  • Retransmit functionality achieved using counter increment feature
  • Collision Detection
    • BUSY signal
  • Power Supply 1.8V or 1.5V
  • Four selectable I/O standards
    • LVTTL (3.3V)
    • Extended HSTL (1.4V to 1.9V)
    • 2.5V LVCMOS
    • 1.8V LVCMOS
  • Upto 200MHz in pipelined mode
  • Selectable Pipeline or Flow-Through mode
  • Burst Counter, Mask & Counter Wrap around features
  • Dedicated Retransmit feature (with RT# pin) enabling repeated access to the same block of memory
  • Collision Detection
    • BUSY signal
    • Readable register to store collision address
    • Busy Address Readback
  • Echo Clocks for reliable data transfer at high speeds
  • Variable Impedance Matching (VIM)