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AN47994 - Interfacing TI OMAPV1030 Processor to Cypress West Bridge® Antioch™ | Cypress Semiconductor

AN47994 - Interfacing TI OMAPV1030 Processor to Cypress West Bridge® Antioch™

Last Updated: 
Nov 23, 2015
Version: 
*B
This is an Obsolete Application Note
The document AN47994 - Interfacing TI OMAPV1030 Processor to Cypress West Bridge® Antioch™ has been marked as obsolete. The obsolete version of this application note is still available with the below description but may not be complete or valid any longer. If you have any questions or require support in regards to the below application note content, please click here and create a technical support case.

Cypress West Bridge® Antioch™ device provides high speed USB peripheral and mass storage control capabilities to the system processor through its host processor port. This application note presents a system example of interfacing a TI OMAPV1030 baseband processor to an Antioch device, using Antioch’s Pseudo-CRAM processor-port (P-port) interface.