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AN4067 - Endpoint FIFO Architecture of EZ-USB FX1/FX2LP™ | Cypress Semiconductor

AN4067 - Endpoint FIFO Architecture of EZ-USB FX1/FX2LP™

Last Updated: 
Nov 23, 2015
Version: 
*C
This is an Obsolete Application Note
The document AN4067 - Endpoint FIFO Architecture of EZ-USB FX1/FX2LP™ has been marked as obsolete. The obsolete version of this application note is still available with the below description but may not be complete or valid any longer. If you have any questions or require support in regards to the below application note content, please click here and create a technical support case.

AN4067 describes the FIFO architecture of the EZ-USB FX1, the full speed USB microcontroller and the EZ-USB FX2LP™, the high-speed USB microcontroller. The purpose of this application note is to help the user understand the very basics of the FX1/FX2LP and get familiar with the terminologies used while describing the data flow in FX1/FX2LP. The application note addresses and discusses the following:

  • Three modes of operation of the FX1/FX2LP
  • Endpoint Configuration and Multiple Buffering
  • Three Domains that form the basic component of the FIFO architecture
  • Arming and committing endpoint buffers
  • Endpoint operation in manual vs. auto mode