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AN15330 - Interfacing Cypress West Bridge® Antioch™ to Marvell® PXA27x Processor | Cypress Semiconductor

AN15330 - Interfacing Cypress West Bridge® Antioch™ to Marvell® PXA27x Processor

Last Updated: 
Oct 27, 2014
Version: 
*E
This is an Obsolete Application Note
The document AN15330 - Interfacing Cypress West Bridge® Antioch™ to Marvell® PXA27x Processor has been marked as obsolete. The obsolete version of this application note is still available with the below description but may not be complete or valid any longer. If you have any questions or require support in regards to the below application note content, please click here and create a technical support case.

West Bridge® Antioch™ provides a processor port (P-Port) that interfaces with the system processor to enable highspeed USB connectivity and mass storage access. This application note presents a system configuration example to interface the Antioch to a Marvell PXA27x processor.

Introduction

The rapid growth of mobile and embedded devices demands high-speed USB connectivity and mass storage capabilities. With that in mind, the Cypress West Bridge Antioch device (CYWB0124AB) was designed to easily enable handset designers to add these functionalities in their designs.