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Adjusting PSoC® Trims for 3.3V and 2.7V Operation - AN2012 | Cypress Semiconductor

Adjusting PSoC® Trims for 3.3V and 2.7V Operation - AN2012

Last Updated: 
Nov 29, 2017
Version: 
*C
This is an Obsolete Application Note
The document Adjusting PSoC® Trims for 3.3V and 2.7V Operation - AN2012 has been marked as obsolete. The obsolete version of this application note is still available with the below description but may not be complete or valid any longer. If you have any questions or require support in regards to the below application note content, please click here and create a technical support case.

For the PSoC® microcontroller to meet the Internal Main Oscillator frequency accuracy and Internal Voltage Reference accuracy specifications, proper settings must be loaded in the associated trim registers. The trim register settings are different for 5V operation (5.25V ≥ VDD ≥ 4.75V), 3.3V operation (3.6V ≥ VDD ≥ 3.0V), and 2.7V operation (2.4V ≥ VDD ≥ 3.0V). Trim values for 5V operation are automatically loaded during power on reset (POR). This application note demonstrates how to set the trim voltages for 5V, 3.3V, and 2.7V operation.