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Slave FIFO GPIF with fast data transfer

Summary: 4 Replies, Latest post by RSKV on 04 Jul 2012 10:02 AM PDT
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clh23047's picture
User
65 posts

Hello, everyone. Now I can run the Slave FIFO Asynchronous example with the evaluation board. I still want to know how to check the transfer speed of the Slave FIFO GPIF. With the UART debugger, I find the data transfer is not so fast in Slave FIFO Asynchronous example. How could I increase the transfer speed and what is the maximum transfer speed we can get?  

Thanks,

Lehua Chen

clh23047's picture
User
65 posts

I made a mistake. The Streamer is working! When I increase the frequency (square wave) at the SLWR to 390K (Packets per Xfer 128; Xfers to Queue 16), I can get the Throughput (700KB/s) and the received data are Successes. According to estimation, the measured throughput is reliable.

 
Now what I need to do is increasing the transfer speed with the Slave FIFO Asynchronous. I am only interest in transferring huge data from the FPGA to GPIF and then to PC. Any suggestions to optimize the Slave FIFO Asynchronous example will be appreciated.
 
Thank you,
Lehua Chen
rskv's picture
Cypress Employee
1134 posts

Hi Lehua Chen,

Good to know that.

Using "burst" you can increase the throughput. I am not sure whether you tried the USBBulkSourceSink example that comes with the SDK. You can look for "CY_FX_EP_BURST_LENGTH" in that project. Also there is a readme.txt to explain the steps needed to do performance optimizations.

Regards,

sai krishna.

clh23047's picture
User
65 posts

Hello, sai Krishna,

Thank you for your reply.
 
I solved the problem now. I also tried Slave FIFO Synchronous example. When the PCLK is connected to 40MHz square wave (limited by the function generator), I get the maximal throughput 115700KB/s. I think this is reasonable.
 
In conclusion, the mistakes made by me are as following:
 
(1) In the Slave FIFO Asynchronous example, I connected the SLWR to constant 0. So the write process can not start. After I connected the SLWR to the function generator, the write process is on. But the frequency on SLWR is only 3KHz, it is two small for the Streamer to check the throughput. Therefore, I always thought the Streamer did not work in the right way.
 
(2) In the Slave FIFO Synchronous example, SLDR can be connected to constant 0 (maybe due to the PCLK). After optimizing as what I did in Bulksourcesink, everything is fine.
 
Thank you for your kind help, Sai Krishna
Lehua Chen
rskv's picture
Cypress Employee
1134 posts

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It’s my pleasure to help you.

Thanks for posting your learnings in the forum so that the other customers will get benefit out of your posts.

Regards,

sai krishna.

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