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Using the Resource Efficient Count7 | Cypress Semiconductor

Using the Resource Efficient Count7

Each UDB has a datapath, control register, status register and 2 PLDs.  An additional resource that is available is a count7.  A count7 is 7-bit down counter that borrows some of the resources from the other parts of the UDB.  Specifically the count7 uses the control register, it uses the mask register of the status register and if a routed load or routed enable is used, then the inputs that would be used by the status register are consumed.  If neither the routed load nor enable are used, then a status register can still be used in the UDB, but the interrupt capability (statusi) is not available.  That means that for the cost of a control register and sometimes a status register you can get the functionality of a 7-bit down counter.

The SimpleCount7Test project demonstrates the simple usage of the count7.  This design instantiates a count7 in Verilog as follows:

  • cy_period: This is the 7-bit value that gets loaded when the counter reaches 0.  The overall period of the counter is (cy_period+1).  In this example the counter counts: 3, 2, 1, 0 for a period of 4.
  • load: The routed load is disabled in this case so a constant 0 (don’t load) is used.
  • enable: The routed enable is disabled so a constant 1 (enabled) is used.

The waveform shows the count sequence that is generated starting from power up.

CNT_START refers to the software enable bit for the count7.  The most common mistake I see with new users of the count7 is forgetting to set the software enable.  The count7 comes up disabled.  Software must write the CNT_START to 1 in the Aux Control register in order to enable the counter.  Refer to the main.c in the example projects.  The first cycle after being enabled the Period register is loaded into the counter and it then begins to count down.  Once it hits 0 the period is reloaded.  The Terminal Count (TC) goes active one cycle after reaching 0.  The TC signal is registered which is the reason for the one cycle delay from the 0 count.

The FullCount7Test project demonstrates more of the features of the count7.  It is instantiates the instance in Verilog as follows:

  • cy_init_value: An initial value other than 0 can be provided.  It will be loaded by software at configuration time.
  • cy_route_ld: Enables the routing of the load signal
  • cy_route_en: Enables the routing of the enable signal

In this design the load and enable signals are connected to the two mechanical buttons on the DVK.  Those buttons are low when pressed, so the inverters on the schematic change the polarity so that pushing the buttons causes enable or load to occur.

The routed hardware enable is in addition to the CNT_START software enable.  Both must be active in order for the counter to count.  The counter counts down on each clock when the enable is high.

The routed hardware load will cause the counter to be reloaded with the period count value on any clock where load is high and enable is also high.  Note that enable must be high in order for the load to occur.

Another note on the load signal is that the load signal when count is 0 will prevent the TC from going active in the next cycle.

That's all there is to using the count7 in your own Verilog component.  When you just need a count7 in a schematic design and to provide examples of how to create APIs around the count7, my next post will be a count7 for the PSoC Sensei library that you can just drop into a schematic.

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