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Using the Datapath for Data Storage | Cypress Semiconductor

Using the Datapath for Data Storage

In an earlier post I provided a component that lets you use the datapath portion of the PSoC 3 / 5 UDB for its FIFO capability.  In this post I’m providing components that let you take advantage of the registers within the datapath for storage.  Each datapath has two 8-bit wide accumulators.  The datapath has just one parallel input and one parallel output path, so only one value can be changed and only one value can be accessed at a time.  The implementation that I’m providing configures the two bytes of storage as two registers in series.  This provides two bytes of storage with a fixed delay from the data being clocked in to the data being clocked out.  In some cases you might also want to store just a single byte and have access to that byte just like a conventional D Flip-Flop.  A second component is provided for that case.

 
To create more storage these components can be configured in a series chain.  An example usage for such a configuration is a filtering operation.  For example the implementation of an average of 8 values filter will require the storage of the last 8 values.  There are several ways that such a filter could be implemented.  The brute force approach would be to store all 8 values in a chain and then add the last 8 values every clock cycle.  There are two disadvantages to this approach.  First this requires access to all 8 values and if the Delay2x8 component is used, only every other value is available.  Secondly the computation of this sum will use 64 inputs to calculate the result and this will consume significant macrocell resources.  An alternative implementation is to keep a running sum where the new value is added to the sum and the value from 8 clocks ago is subtracted from the sum.  This fits well with the Delay2x8 component and uses far less macrocell resources.  I’ve provided this example: DelayTest.  You’ll also need the latest PSoC Sensei component library to have access to the Delay components.  Below is how the Delay2x8 components are chained and connected to implement the average function.
 
 
The average function has been written using Verilog and then synthesized into the macrocells by Creator.  As you can see from the report file, this implementation is balanced between Datapath and Macrocell resources consuming about 20% of the digital resources in the device.
 
 
The implementation of the average filter simply adds in the new value and subtracts out the old value and then shifts by 3 (divide by 8) to provide the result.
 
 
In the example design provided I’ve used control and status registers to test the hardware operation without needing hardware test equipment.  To accomplish this I’ve used an edge detector to enable the components for a single clock cycle under program control.  That allows the hardware to step forward as the program that controls the test progresses.
 
 
To test out this circuit you can bring the example up in the debugger.  Then set breakpoints and also add a Watch on the i and avg variables.  The picture below shows the results during the debug of an incrementing sequence.
 
 

Comments

david_dlp's picture

Hello Sensei! This is a great article - thanks! I am working on a complex PSoC5 design that has me stuck at the moment, and I think I am going to try your UDB delay blocks as 8 bit registers in place of my 8 bit register verilog components. Warp keeps optimizing things out of my design and I am struggling to understand why, and maybe these UDB components will work better. The report file is not clear enough for me to understand what is really going on. Is there a way to view the synthesized design to try and understand what is really coming out of Warp? Also, is there a way to force Warp to keep certain components in my design? I tried the (* KEEP=TRUE *) attribute but it seems like this is not supported.

bjbu's picture

I expect that Warp won't eliminate these delay elements, but it is not likely that Warp was eliminating something in RTL that was properly used. Typically when Warp eliminates something that is a good indication that you've done something wrong.

If you would like to send me your original design including the RTL code in question I'll take a quick look at it.

PSoC Sensei - bjbu@cypress.com

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