PSoC Creator is no longer Beta. It made the leap to a Production Release this week. It’s available for download now. If you already have a Beta version installed you can just upgrade with the installer from the Beta release. If you haven’t installed PSoC Creator yet, then you can find it at www.cypress.com/go/psoccreator and then click the Download button.
With the Production release there are some new features and components. This post will discuss how to synchronize signals including how to use the new Sync component.
PSoC 3 and 5 have considerable flexibility in the clocking mechanisms that are available. Throughout the digital logic array (UDB array) there are 9 low skew clocks available. One of these is always the bus clock (BUS_CLK). This is the clock that the system bus that runs throughout the device runs at. By default this is also the speed that the CPU is running at (PSoC 3 can support a divided CPU clock). There is another clock called the master clock (MASTER_CLK). This is the fastest clock in the system. It is possible to have BUS_CLK be divided down from MASTER_CLK, but I strongly encourage that you always have this divider set to 1 (that is the default). If you follow that recommendation BUS_CLK, MASTER_CLK and the CPU_CLK will all be the same frequency and the fastest clocks in the system. The other 8 clocks will be divided down versions of any of the clocks in the system. These clocks by default will be synchronized to MASTER_CLK. This is controlled by a check box in the clock customizer.
You will generally want all your clocks synchronized to MASTER_CLK. That will allow easy communication between these clock domains and communication with the CPU or DMA. With all these clocks synchronous to MASTER_CLK a signal crossing between the domains will need to meet setup timing requirements within a MASTER_CLK period. When going from one clock domain to a slower clock domain the signal will need to be held long enough that it will be sampled by the slower clock domain, but there aren’t any asynchronous clock crossing issues.
Some signals in your system will likely come from sources that are asynchronous to the clock domain where they are used. The most common source for an asynchronous signal is an input pin. By default digital input pins are synchronized. This checkbox causes the input signal to be synchronized to BUS_CLK.
Synchronization is done by a double synchronizer. Logically a double synchronizer is implemented as two back to back flip-flops.
The theory behind this structure is that the signal may fail to meet the setup or hold time of the first flip-flop causing it to go to a metastable state. If that condition occurs it will settle to either 0 or 1 before the value gets clocked into the second flip-flop, so the value from the second flip-flop can be used with confidence that it will change only on the clock edge. A double synchronizer will introduce from 1 to 2 clock cycles of delay on the incoming signal.
The synchronizer for the input pin will be implemented directly at the pin if BUS_CLK is less than or equal to 33 MHz, and it will be implemented within the UDB array for higher speed clocks. When implemented within the array a special configuration of a Status register is used that can synchronize up to 4 signals to the same clock. PSoC Creator will automatically pack signals synchronized to the same clock. In either case the synchronization is done with BUS_CLK.
Synchronizing to BUS_CLK provides lower latency than synchronizing to a lower speed clock, but it places tighter timing constraints. Ideally signals should be synchronized to the same clock domain where they will be used. This can be accomplished by using the new Sync component which can be found in the component catalog in the System folder. For a pin the Sync can be used in place of the BUS_CLK synchronizer by turning off synchronization on the pin component and using the Sync component. The clock for the Sync component can be any clock in the system.
The Sync component is always implemented with the special mode of the Status register. When reviewing the report file for resources utilized you’ll find separate entries for Status and Sync Cells, but they are using the same resources. To account for this the number listed as the Max Sync Cells is calculated as 4 times the Free Status registers.