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The PSoC Sensei Component Library | Cypress Semiconductor

The PSoC Sensei Component Library

One of the powerful features of PSoC Creator is the ability to use libraries of components.  Cypress ships a library of core components with PSoC Creator, but you can create your own library or use a library from another source.  Starting with this blog post I'll be providing a library of components that I build as part of this blog.  You can use this library in your projects or you can use these components as examples to help you create your own unique components.

All the components in the library will be versioned.  For example the first component in the library is FIFOIn v1.0.  If I make functional changes to that component I'll create a new version.  Both the new version and all older versions will continue to be in the library.  You can make the decision on when you want to upgrade to a newer version of a component.  This is the same methodology used with the core library.  The Component Update Tool can be used to choose the version of a component you want to use.

Long ago when I last posted to the blog (I'll be posting more frequently) I provided an 8-bit wide FIFO component.  Even though PSoC 3 has an 8-bit processor, much of the infrastructure in the chip is either 16-bits or 32-bits wide.  In particular the DMA path from the UDBs to SRAM supports 16-bit transfers.  This means that you can get twice the performance by using a 16-bit wide version.  The component in the PSoC Sensei library supports both 8 and 16-bit operation.  The example that I've provided uses the component in 16-bit mode.

In this example there is a 16-bit free running counter providing the input data.  The Timer is used to indicate when to capture a word from the counter.  The Timer component will produce a single cycle pulse every time it counts down to 0.  This is used to control the rate that data is sampled.  As configured it causes a counter value to be captured every 9 cycles.  This is as fast as the DMA engine can capture a single one word burst of data from the UDBs.  This is true whether it is capturing an 8-bit word or a 16-bit word.  These 9 cycles are made up of 7 cycles of overhead and 2 cycles to transfer the word.

If you run the design in the debugger you can watch the buf[] array and see the values that are captured.  The starting value is dependent on when the components are enabled, but each entry after the first should be 9 more than the last.  Below is a capture from the debugger:

As described, the maximum rate is dependent on the overhead cycles and the transfer cycles.  If you need to transfer words faster than 9 cycles per word, then you can transfer more than one word at a time.  This can be accomplished by setting the FIFO up to cause a DMA to occur once the FIFO is at least half full.  This indicates that there are at least 2 words available.  That configuration is done by configuring the component as shown:

Now that you know that at least two words are available you can change the setup of the DMA to do 4 byte bursts (2 words) instead of 2 byte bursts.  That is done in the DMAInitialize() function call with the first parameter as shown here:

Now the system is able to transfer 2 words every 11 cycles.  These cycles are made up of the same 7 overhead cycles and then 4 cycles for the transfer of the two words.  That makes the average rate 5.5 cycles per word.  The last change to make is to change the period of the Timer component.  Update that from a period of 9 to a period of 6.  Now a word will be put in the FIFO every 6 cycles.  The result is shown from the debuggger:

Attached is the example project and the library.  The example is dependent on the library (Project->Dependencies...).  PSoC Creator puts dependencies in a project relative to the location of the project.  If you unzip both of these files in the same parent directory, then the example will be able to find the library.  If you place the library somewhere else, then you will need to update the dependency to point to the right place.  I've included a complete datasheet with the FIFOIn component, so take a look at the datasheet and at this example for more details on the use of this component.

Example FIFOIn 16-bit project:  FIFOIn16Example.zip

PSoC Sensei Component Library: PSoCSenseiLibrary.zip

Comments

oakm_ukr's picture

Brad,

You have to enable interrupt generation logic within statusi register.

Orest

robertseczkowski's picture

DMAInitialize for PSOC 3 should be SRAM_BASE and PERIPH_BASE
(4,1,0,0) imply that SRAM_BASE = PERIPH_BASE = 0
robert

robertseczkowski's picture

DMAInitialize is reg on SRC side and SRAM on the other. So Dma Initialize can not point to ...0,0);
as these are different regions.
Secondly Component don't seem to interact with it's properties as it's missing correct file (.resx)

bjbu's picture

Yes, for PSoC3 the SRAM_BASE and PERIPH_BASE are 0. These arguments are the upper 16-bits of a 32-bit address. On PSoC3 the only thing that isn't in the first 64K of address space that you might want to use with a DMA is the Flash memory. Everything else should have 0 for the upper 16-bits of address. It is also important that you don't use the HI16() macro with a variable address like you should with PSoC5. The issue with doing that on PSoC3 is that the Keil compiler embeds bits in the upper byte of the address to distinguish various pointer types. That results in a value that is not 0 when taking the HI16 of a variable address and that will fail.

A .resx file is not applicable for this component. I've not used a customizer with any of the components that I've provided with this blog. Most components can be handled well with the default parameter configuration GUI that is provided by Creator directly. The default GUI should be displayed when you double click the component.

dStar's picture

Hi,

this component is pretty cool!

is there a complementary "FifoOut16"-component implemented and available aswell ?

Thanks

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