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PSoC 4 Chained Clocks | Cypress Semiconductor

PSoC 4 Chained Clocks

With PSoC 4 there is another added clocking feature, chained clocks. The clock dividers in PSoC 4 come as sets of 3 clock dividers. The current devices have a total of 4 sets of 3, so 12 dividers in total.  Any of these 12 clocks can be used to drive one or more of the 16 possible destinations.
 
The clocks are configured in sets of 3 to allow for chaining. I'll refer to the three dividers as A, B and C. Divider A is always fed by the High Frequency (HFCLK) clock source. Divider B can be fed by either HFCLK or divider A. Divider C can be fed by either HFCLK or divider B. Fortunately you don't generally need to worry about that level of detail. Creator knows about chained clocks and it will handle which clock dividers to use.
 
The simplest usage of chained clocks is when you need a divider that is larger than a single divider supports. The dividers are 16 bits. If you need to divide by more than 64K, then you'll need two dividers to be chained. Creator will do this automatically. For example with a 24 MHz HFCLK a single divider cannot be used to create a 100 Hz clock. That requires a divide by 240,000. If a clock is placed in this design configured for 100 Hz, then Creator will generate this clock using two chained clock dividers and show this as a divide by 240000:
 
 
 
What Creator actually did was setup two chained dividers.  The first divider divides by 500 and the second divider divides by an additional 480 with the result being a divide by 240,000. In this case there are many possible choices for the two factors, but not all divider values are possible. Creator will determine the two clock divider combination that results in the closest output frequency to what is requested.
 
The other application for chained dividers is when two clocks must be aligned. For example if a design has a 2 MHz clock (divide by 12) and a 1 MHz clock (divide by 24), then when the clocks are started the alignment between the waveforms can't be guaranteed. These are generated by two independent dividers. All the edges of these clocks will happen at the rising edge of the 24 Mhz clock, but the alignment between these two clocks will depend on the exact amount of time between when each of the dividers is started. This relationship will also change when the clocks are stopped and restarted. The following waveform is just one possible resulting alignment:
 
 
If the design requires that the edges of the 1 MHz clock always occur on the rising edge of the 2 MHz clock, then chained clocks can be used to meet this requirement. This requires first creating a design wide clock running at 2 MHz. From the Design Wide Resources (DWR) clock tab select the Add Design-Wide Clock button at the top corner of the screen:
 
 
Then name that clock and configure it for 2 MHz:
 
 
Now use this design wide clock to create the two clocks.  First, the 2 MHz clock in the design should just be configured to use this existing Design Wide clock. In this case an additional divider is not used.
 
 
Next, the 1 MHz clock configuration needs to be changed to use the Design Wide clock as the input for the divider.  It still needs to have a new clock divider to be used in order to create that divide by 2 clock:
 
 
The DWR clock page will now show this configuration as follows:
 
 
Creator handles all the details of putting these two dividers into adjacent dividers and chaining them.
 
The resulting waveform now shows the clocks aligned as expected:
 

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